//////////////////////////////////////////////////////////////////////////////
//
//  PCIE Macros
//
//  Macros for general PCIE usage
//
//  Original Author: YEJIACHENG ZHANG
//  Current Owner:   YEJIACHENG ZHANG
//
//////////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2013 Synopsys, Inc.  All rights reserved.
//
// SYNOPSYS CONFIDENTIAL - This is an unpublished, proprietary work of
// Synopsys, Inc., and is fully protected under copyright and trade secret
// laws.  You may not view, use, disclose, copy, or distribute this file or
// any information contained herein except pursuant to a valid written
// This program is the property of Accelerant Networks and is furnished
// pursuant to a written license agreement. It may not be used, reproduced,
// or disclosed to others except in accordance with the terms and conditions
// of that agreement.
//
//////////////////////////////////////////////////////////////////////////////
//
//    Perforce Information
//    $Author: bimalp $
//    $File: //dwh/up16/main/dev/pma/include/kcodes.v $
//    $DateTime: 2013/06/11 09:52:51 $
//    $Revision: #2 $
//
//////////////////////////////////////////////////////////////////////////////

`ifndef KCODES_V
`define KCODES_V

// K Codes
 `define KCODE_8B_COM 8'hBC // K28.5
 `define KCODE_8B_FTS 8'h3C // K28.1
 `define KCODE_8B_SDP 8'h5C // K28.2
 `define KCODE_8B_IDL 8'h7C //
 `define KCODE_8B_PAD 8'hF7 //
 `define KCODE_8B_STP 8'hFB //
 `define KCODE_8B_END 8'hFD //
 `define KCODE_8B_EDB 8'hFE //
 `define KCODE_8B_SKP 8'h1C // K28.0
 `define KCODE_8B_EIE 8'hFC // K28.7

 `define KCODE_10B_COM 10'h0FA // K28.5
 `define KCODE_10B_FTS 10'h0F9 // K28.1
 `define KCODE_10B_SDP 10'h0F5 // K28.2
 `define KCODE_10B_IDL 10'h0F3 // K28.3
 `define KCODE_10B_SKP 10'h0F4 // K28.0
 `define KCODE_10B_END 10'h2E8 // K29.7
 `define KCODE_10B_EIE 10'h307 // K28.7
 `define KCODE_10B_PAD 10'h3A8 // K23.7
 `define DCODE_10B_TS1 10'h155 // D10.2
 `define DCODE_10B_TS2 10'h295 // D5.2
 `define DCODE_10B_ZRO 10'h274 // D0.0
 

//------------------------------------------------------------------------------
// GEN3 Tokens
//------------------------------------------------------------------------------
  
// Logical Idle  Ordered Set
// from PCI_Express_Base_r3.0_v0.7_Chapter04_06feb09.pdf, p40
 `define TOKEN_LOGICAL_IDLE 8'h00

// Start Data Link Layer Packet Ordered Set
// from PCI_Express_Base_r3.0_v0.7_Chapter04_06feb09.pdf, p40
 `define TOKEN_SDP_0 8'hF0 // Start DLLP (SDP) Byte 0
 `define TOKEN_SDP_1 8'hAB // Start DLLP (SDP) Byte 1

// End of Data Stream Ordered Set
// from PCI_Express_Base_r3.0_v0.7_Chapter04_06feb09.pdf, p40
 `define TOKEN_EDS_0 8'h1F // End of Data Stream Byte 0
 `define TOKEN_EDS_1 8'h80 // End of Data Stream Byte 1
 `define TOKEN_EDS_2 8'h90 // End of Data Stream Byte 2
 `define TOKEN_EDS_3 8'h00 // End of Data Stream Byte 3

 `define TOKEN_EDB 8'b11000000

// Electrical Idle Ordered Set
// from PCI_Express_Base_r3.0_v0.7_Chapter04_06feb09.pdf
 `define TOKEN_EIOS_0 8'h66   // EIOS Bytes 0-15

// Start of Data Stream
// from PCI_Express_Base_r3.0_v0.9_20July10.pdf
 `define TOKEN_SDS_0 8'hE1   // SDS Byte 0
 `define TOKEN_SDS_1 8'h55   // SDS Bytes 1-15

// Electircal Idle Exit Ordered Set
// from PCI_Express_Base_r3.0_v0.7_Chapter04_06feb09.pdf
// Electircal Idle Exit Ordered Set
// from PCI_Express_Base_r3.0_v0.7_Chapter04_06feb09.pdf
 `define TOKEN_EIEOS_0 8'h00   // FTS Bytes 0,2,4,6,8,10,12,14
 `define TOKEN_EIEOS_1 8'hFF   // FTS Bytes 1,3,5,7,9,11,13,15

// Fast Training Sequence Ordered Set
// from PCI_Express_Base_r3.0_v0.7_Chapter04_06feb09.pdf
 `define TOKEN_FTS_0 8'h55   // FTS Byte 0 
 `define TOKEN_FTS_1 8'h47
 `define TOKEN_FTS_2 8'h4E
 `define TOKEN_FTS_3 8'hC7
 `define TOKEN_FTS_4 8'hCC
 `define TOKEN_FTS_5 8'hC6
 `define TOKEN_FTS_6 8'hC9
 `define TOKEN_FTS_7 8'h25
 `define TOKEN_FTS_8 8'h6E
 `define TOKEN_FTS_9 8'hEC
 `define TOKEN_FTS_10 8'h88
 `define TOKEN_FTS_11 8'h7F
 `define TOKEN_FTS_12 8'h80
 `define TOKEN_FTS_13 8'h8D
 `define TOKEN_FTS_14 8'h8B 
 `define TOKEN_FTS_15 8'h8E   // FTS Byte 15

// Training Set 1 Ordered Set
// from PCI_Express_Base_r3.0_v0.7_Chapter04_06feb09.pdf
 `define TOKEN_TS1_0 8'h1E   // TS1 Byte 0 for gen 3
 `define TOKEN_TS1_1 8'h00   // Link#
 `define TOKEN_TS1_2 8'hF7   // PAD?
 `define TOKEN_TS1_3 8'h04   // N_FTS: number of FTS required by RX.
 `define TOKEN_TS1_4 8'hCE   // Support all rates
 `define TOKEN_TS1_5 8'h00   // Disable Hot Reset, Loopback, etc.
 `define TOKEN_TS1_6 8'h4A

 `define TOKEN_TS1_14_POS 8'hDF
 `define TOKEN_TS1_14_NEG 8'h20
 `define TOKEN_TS1_15_POS 8'hF7
 `define TOKEN_TS1_15_NEG 8'h08

// TS2 definition from PCIe Base Specification r3.0 Nov10,2010
`define TOKEN_TS2_0 8'h2D   // TS2 Byte 0 for gen 3
`define TOKEN_TS2_1 8'h00   // Link#
`define TOKEN_TS2_2 8'hF7   // PAD?
`define TOKEN_TS2_3 8'h04   // N_FTS: number of FTS required by RX.
`define TOKEN_TS2_4 8'hCE   // Support all rates
`define TOKEN_TS2_5 8'h00   // Disable Hot Reset, Loopback, etc.
`define TOKEN_TS2_6 8'h00   // Disable Quiesce Guarentee, Request Equalization
`define TOKEN_TS2_7 8'h45   // 45h.  DC balance symbols may be inserted instead on Symbol 14 and Symbol 15

 `define GEN3_DATA_SYNCHEADER 2'b10
 `define GEN3_OS_SYNCHEADER   2'b01
 `define GEN3_2B_DATA_SYNC    2'b10
 `define GEN3_2B_OS_SYNC      2'b01
 `define GEN3_2B_DUM_SYNC     2'b11
 `define GEN3_2B_BODY_SYNC    2'b00

// SKP Ordered Set
// from PCI_Express_Base_r3.0_v0.7_Chapter04_06feb09.pdf
 `define TOKEN_SKP          8'hAA
 `define TOKEN_SKP_END      8'hE1
 `define TOKEN_SKP_LFSR     8'h00

`endif // KCODES_V
